1. Field of the Invention
The present invention relates to a field effect transistor, and more particularly to a Schottky-gate field effect transistor capable of operating at a high speed and in a high frequency band.
2. Description of Related Art
Metal semiconductor field effect transistors or Schottky-gate field effect transistors (hereinafter abbreviated "MESFET") have been widely and praisefully used as an amplification or oscillation circuit element for their excellent performance especially in the range of super-high frequency. Also, these semiconductor devices have been built in super-high speed integrated circuits, and their excellent performance is well known.
FIG. 1 shows the structure of a MESFET which is used most widely. As shown in the drawing, a semiconductor crystal layer 22 having a relatively high conductivity (commonly called "active layer") is formed on a high-resistive resistive or semi-insulative semiconductor crystal substrate 21, and a Schottky-contact gate electrode 23 (commonly called "Schottky gate electrode"), an ohmic-contact source electrode 24 and an ohmic-contact drain electrode 25 are formed on the surface of the active layer 22. In operation, the thickness of the depletion region 26 expanding downward from the Schottky gate electrode 23 is controlled by varying the voltage applied to the Schottky gate electrode 23, thereby controlling the electric current flowing from the source electrode 24 to the drain electrode 25.
Transconductance "g.sub.m " and cutoff frequency "f.sub.T are used as the figures of merit of a MESFET. These figures of merit are given by ##EQU1## where "Lg" stands for the length of the gate electrode; "Z" for the width of the gate electrode; ".mu." for the mobility of carriers; "a" for the thickness of the active layer; ".epsilon." for the dielectric constant of the semiconductor; "Vg" for the voltage applied to the gate electrode; "Vth" for the threshold voltage of the MESFET and "Cgs" for the capacitance appearing between the gate and source electrodes.
The performance of a MESFET will be improved with the increase of "g.sub.m " and "f.sub.T ".
As is apparent from the above mathematical statements, transconductance "g.sub.m " can be increased by shortening the gate length "Lg". Simultaneously, the capacitance "Cgs" between the gate and source electrodes of the semiconductor device decreases, and hence the cutoff frequency increases.
Incidentally, in the structure of the MESFET as shown in FIG. 2, a parasitic series resistance "Rs" appears between the source and Schottky gate electrodes of the semiconductor device, and if the parasitic resistance "Rs" is large, the electric field "E" between these electrodes will decrease because of a large voltage drop occurring across the parasitic resistance "Rs", accordingly lowering the transconductance "g.sub.m ". In general, the transconductance "g.sub.m " is given by: ##EQU2## where "g.sub.mo " stands for an intrinsic transconductance which would appear if there were no parasitic series resistance "Rs".
It is found that GaAs and any other semiconductor material which has elevated surface states are liable to cause a relatively high parasitic resistance "Rs" to appear.
As is apparent from the above, the performance of a MESFET can be improved by shortening the gate length "Lg" of the device and by reducing the parasitic series resistance "Rs" between the source and Schottky gate of the semiconductor device. In an attempt to reduce the gate length of the device, it has been proposed that:
(1) use is made of a submicron resist pattern prepared by a direct electron beam lithography.
Also, in an attempt to reduce the parasitic series resistance "Rs" between the source and Schottky gate electrodes, a variety of arts have been proposed:
(2) the region other than the Schottky gate electrode is ion-implanted for activations;
(3) a refractory Schottky gate is formed on a substrate, and then the substrate is subjected to ion-implantation by using the gate electrode as mask for self-alignment (See N. YOKOYAMA, ISSCC Digest of Technical Page, P. 218, 1981);
(4) necessary ion-implantation is effected by using a dummy gate electrode as a mask, and then the pattern is reversely replicated to form a Schottky gate electode (See K. Yamasaki, Electronics Letters Vol. 18, p. 120); and
(5) the distance between the source and Schottky gate electrodes is reduced (A. Higashisaka, Extended Abstracts of the 15th conf. on Solid State Device & Material, 1983, p. 69).
Some details of these proposals (2) to (5) are given below:
As regards Proposal (2), a semiconductor substrate is ion-implanted with impurities, and then the semiconductor substrate is subjected to annealing, thereby activating the impurity in the semiconductor substrate to provide relatively high conductive regions, resulting in decrease of the parasitic series-resistance "Rs" between the source and Schottky electrodes of the semiconductor device.
As regards Proposal 3, as shown in FIG. 2, a refractory gate metal 27 is formed on the surface of the active layer 22, and an ion-implantation is effected by using the gate metal 27 as a mask. Then, the semiconductor substrate thus ion-implanted is subjected to annealing, and thereafter source and drain electrodes are formed.
As for Proposal 4, as shown in FIG. 3, a dummy gate 28 which is made of a material appropriate for the purpose of masking for later ion-implantation, is formed on the active layer 22. The semiconductor substrate is heavily ion-implanted with impurity, and then it is annealed. Thereafter, patterning is reversed to form source and drain electrodes first, and a Schottky gate electrode next.
As for Proposal 5, as shown in FIG. 4, a Schottky gate electrode 23 is formed on the active layer 22, and then the whole upper surface of the semiconductor substrate is coated with an insulation material 30. The insulation coating 30 is removed from the upper surface of the semiconductor substrate other than the side wall of the Schottky gate electrode 23. Then, the whole upper surface of the semiconductor substrate is coated with an ohmic-contact metal 31, and finally, source and drain electrodes are formed by removing the metal from the outside of the Schottky electrode.
Since isotropic insulation coating is used as a matter of course, the outside of the Schottky gate electrode should be coated with an insulating material as thick as the flat surface of the semiconductor substrate. Also, as a matter of concern anisotropic etching such as reactive ion-etching should be used, assuring that the insulation coating be removed only the from the horizontal surface of the semiconductor substrate, leaving the insulation coating around the Schottky gate electrode. Thus, the source and drain electrodes are separated from the Schottky gate electrode by the thickness of the insulation coating. Eventually, they are brought as close as practically possible to the Schottky gate.
However, Proposal 1 requires advanced technique, and as a matter of fact its throughput is low, not permitting the reduction to practical use.
Specifically, the proposed method cannot be applied to a substrate having a relatively high resistance such as a GaAs substrate without using certain special arts. Accordingly, application of the same is limited.
Proposal 2 has following defects: ion-implantation and subsequent activation are liable to cause the high-concentration region to expand as far as the Schottky gate electrode, thereby lowering the yielding voltage of the Schottky gate, and increasing the capacitance between the source and Schottky gate electrodes. Accordingly, the performance of such MESFET lowers. These defects, however, can be reduced by performing necessary patterning alignment on registration with exactness. Optical exposing apparatus now available, however, cannot permit such exact alignment or registration required.
Proposal 3 reduces the difficulty of patterning alignment or registration to possible minimum with recourse to self-alignment or registration. The proposed method, however, requires ion-implantation and subsequent annealing, which is effected after forming a Schottky gate electrode. In annealing the semi-fabricated device is heated at an elevated temperature. This disadvantageously limits the kinds of material of which the Schottky gate is made.
Proposal 4 is advantageously free of the difficulty of patterning alignment or registration, as is the case with Proposal 3. Also, advantageously the Schottky gate electrode is formed after annealing, thus putting no limitation to the selection of the material of which the Schottky gate is made. However, patterning reversal requires complicated processes, and still disadvantgeously a Schottky gate electrode at a submicron size is difficult to be formed.
Proposal 5 permits the closest possible arrangement of the drain and Schottky gate electrodes, which, in fact, are separated by the thickness of the insulation coating around the Schottky gate. In this connection, if defect should appear in the thin insulation coating, the semiconductor device would be liable to break down electrically when used. Therefore, if such MESFETs are built in integrated circuits, the dead loss of production will inevitably rise. The layer lying under the ohmic-contact source and drain electrodes is not heavily doped with impurities, thus not permitting the decrease of the contact resistance. As a result, the parasitic series resistance cannot be reduced as much as required.